FPGA BASED OPTIMAL DESIGN AND IMPLEMENTATION OF 32-BIT ASYNCHRONOUS MICROPROCESSOR (Record no. 21008)
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000 -LEADER | |
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fixed length control field | 00411nam a2200145Ia 4500 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 210212s9999 xx 000 0 und d |
041 ## - LANGUAGE CODE | |
Language code of text/sound track or separate title | eng |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | ARCHANA RANI |
245 ## - TITLE STATEMENT | |
Title | FPGA BASED OPTIMAL DESIGN AND IMPLEMENTATION OF 32-BIT ASYNCHRONOUS MICROPROCESSOR |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Date of publication, distribution, etc. | 2019 |
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) | |
Topical term or geographic name as entry element | FET |
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) | |
Topical term or geographic name as entry element | PH.D LONG SYNOPSIS |
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) | |
Topical term or geographic name as entry element | Electronics and Communication Engineering |
Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Barcode | Date last seen | Bill Date | Koha item type |
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MRIIRS | MRIIRS | Reference | 29/07/2019 | TS29 | 23/03/2022 | 23/03/2022 | MRIU Thesis Synopsis |